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Physical failure analysis (PFA) techniques for ICs are:
        i) Optical microscopes
        ii) Scanning electron microscopes (SEM) and EDS
        iii) Focused ion beam (FIB)
        iv) TEM, EDS, and EELS
            iv.a) TEM-EDS: A typical approach for evaluating defect sources at low concentration in semiconductor devices[2]
            iv.b) TEM-EELS: A typical approach for evaluating defect sources at low concentration in semiconductor devices[2]
        v) RIE dry etch
        vi) Chemical wet etch (including junction staining)
        vii) Auger
        viii) SIMS
            viii.a) Time-of-flight SIMS (ToF SIMS): A typical approach for evaluating defect sources at low concentration in semiconductor devices[2]
        ix) Inductively coupled plasma-mass spectroscopy (ICP-MS): A typical approach for evaluating defect sources at low concentration in semiconductor devices[2]
        x) XPS
        xi) FTIR
        xii) AFM
            xii.a) C-AFM (conductive atomic force microscopy)
        xiii) Parallel lapping tools (die and package level)
        xiv) Wire bonder/reball/decapsulation tools

Physical failure analysis (PFA) of advanced technology nodes mainly face three main challenges:
        i) Shrinking dimensions require to get sufficient resolution to observe the defects.
        ii) The chemical complexity of deposited layers may lead to misinterpretation of the analyzed faults.
        iii) Sample preparation of small structures.

Furthermore, in many cases, the physical failure analysis is time-consuming and is very difficult to be interpreted since the structural results cannot clearly explain or match electrical characteristics of the analyzed devices.

Table 2824. Examples of physical failure analysis of IC devices.

Technique	Product	Measurements/results	Comments	Reference
Cross-section and planar TEM	DRAM cells	Gate CD, gate trench depth, spacer SiN thickness, gate oxide thickness, contact CD, contact recess value, active CD, distance of each active, overlap dimension of contact with active, the angles of actives in retention weak DRAM cells and junction leakage		[1]
Staining+TEM/SEM	Doping	Observation of non-visual dopant missing	EM samples need to be very clean	[5]
APT	MOSFET-based device	Carbon segregated at gate oxide/Si substrate interface	Non-visual under TEM-EDS or EELS	[2]
C-AFM + simulation	Transistor	Missing LDD at the drain of a transistor	Such failures (e.g. erratic defects) are non-visual under TEM or SEM	[3]
SEM-based nano-probing (EBAC)	All ICs	Reveal both non-visual and visual failure mechanisms		[4]

[1] Sung Ho Lee, Yong Ho Yoo, Tae Jung Park, Jin Choi, Ju Hyeon Ahn, Seok Sik Kim, Chang-Jin Kang, Seok Woo Nam, Joo Young Lee, Gyo Young Jin, Samsung Electronics Co., Ltd, DRAM Static Refresh Weak Cell Characterization and Structure Analysis, ISTFA Conference Proceedings of the 37th International Symposium, 2011.
[2] Ju-heon Kim, Euna Ok, Hyunmi Sim, Dongkeun Na, Ho Seok Song, Dae Hyun Kim, Yong-beom Cho, Seok-jun Won, Tae-Soo Park, Samsung Electronics Co., Ltd, Impact of carbon on threshold voltage shift in MOSFET studied by 3D atom probe tomography, Proceedings from the 43rd International Symposium for Testing and Failure Analysis, ISTFA 2017.
[3] Cha-Ming Shen, Tsan-Chen Chuang, Shi-Chen Lin, et al., Combining the Nano-Probing Technique with Mathematics to Model and Identify Non-Visual Failures, ISTFA 2007 Proceedings of the 33rd ISTFA, 2007.
[4] Suk Min Kim, Jung Ho Lee, Jong Hak Lee, Hyung Ki Kim, Myung Sick Chang, Jung Hoon Lee, and Sung Joo Hong, R&D Hynix Semiconductor Inc, Failure Analysis of Single Shared Column Fail in DRAM Using Nano-Probing Technique, ISTFA 2008: Proceedings from the 34th International Symposium for Testing and Failure Analysis, Oregon USA.
[5] Y. Liao, J.Y. Degorce, J. Belisle, M. Meunier, 2D dopant determination in laser-diffused Si resistors using dopant-selective etching, Journal of The Electrochemical Society 153 (1), G16-G22.




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