| A 6T SRAM (Static Random-Access Memory) is a digital component. It operates with binary data—storing bits as either a '0' or '1'—and its internal circuits consist of transistors arranged to form bistable latches, which inherently function digitally. The 6T SRAM cell stores a single bit of data using six transistors, with four of them forming two cross-coupled inverters that create two stable states representing 0 and 1, while the remaining two act as access transistors to manage read and write operations. As shown in Figure 0162a, SRAM has three input ports (BL, BLB,WL) and two output ports (Q,QB). The word line (WL) enables the cell by controlling these access transistors, allowing data transfer through the bit lines (BL and BL bar) during both reading and writing. Although only one bit line is required, both the signal and its inverse are typically used to enhance noise margins.
Figure 0162a illustrates the layout and equivalent circuit of a 6T SRAM cell embedded in a 0.25-μm generation microprocessor. [1] The left side of the figure shows the physical layout of the SRAM cell, and the right side shows the equivalent circuit schematic. This SRAM cell design is used in an application for high-frequency and low-voltage modes.
In a typical 6T SRAM cell, there are both NMOS and PMOS transistors. M5 and M6 are access transistors, M1 and M3 pull up, M2 and M4 are pull down transistors. That is, the cell consists of:
- Two load PMOS transistors (or sometimes high-resistive poly load elements in older SRAM designs) - These act as pull-up devices in the storage nodes. In Figure 0162a, Ld-PMOS stands for the load PMOS transistor in the SRAM cell. The Ld-PMOS provides a load to the cell and plays a role in maintaining the voltage at the storage nodes, essential for the retention of data in the SRAM cell. The characteristics of the Ld-PMOS, such as its threshold voltage and transconductance, significantly influence cell stability, especially under low-voltage and high-frequency operation conditions. The load PMOS transistors provide a connection to Vcc (supply voltage) to maintain the storage node at a high voltage when storing a "1".
- Two driver NMOS transistors - These provide the main driving capability for holding the stored data (in a flip-flop configuration). In Figure 0162a, Dr-MOS typically refers to the driver MOSFET in the SRAM cell, which is responsible for driving the output or stabilizing the bit stored in the cell. In SRAM circuits, Dr-MOS devices are crucial for maintaining data stability during read and write operations. The driver NMOS transistors help maintain the storage node at a low voltage (ground) when storing a "0".
- Two access NMOS transistors - These connect the cell to the bit lines during read and write operations, controlled by the word line
In a typical SRAM cell, the two load PMOS transistors and two driver NMOS transistors are arranged to form two cross-coupled inverters, which create a bistable latch. This bistable configuration is stable in two states, allowing it to hold a single bit of data (either a 0 or a 1) as long as power is supplied: - Each inverter output is connected to the input of the other, creating a feedback loop that reinforces the stored state.
- When one node of the cell is high (logic 1), the other node is low (logic 0), and vice versa.
- This cross-coupled configuration maintains the state even without refreshing, which is why SRAM is "static" and can hold its data continuously as long as it remains powered.
Figure 0162a. 6T SRAM cell layout embedded on a 0.25-μm generation microprocessor (left) and its equivalent circuit (right). Adapted from [1] |
SRAM has three primary operations:
- Hold Operation:
In the hold operation, both access transistors are turned off (M5 = M6 = 0). Due to the presence of the latching element in SRAM, the cell maintains its stored state without any change.
- Read Operation:
For the read operation, both bit lines (BL and BLbar) are precharged to VDD, and the access transistors are turned on (M5 = M6 = 1). Depending on the stored data value, one of the bit lines discharges, creating a voltage difference between the two bit lines. This difference is detected by a sense amplifier, allowing us to identify the data stored in memory.
- Write Operation:
To perform the write operation, the data to be written is applied to the bit line, and the access transistors are turned on (M5 = M6 = 1). This setup enables the data to be written into the memory cell.
In a standard SRAM bitcell, two cross-coupled inverters form a stable latch as shown in Figure 0162b. This structure is often referred to as a "bitcell" because it stores one bit. When a node in the bitcell, e.g. Q holds a logic level of 1, the inverter connected to it will drive the complementary node, QB, to 0. This 0 at QB serves as the input to the second inverter, whose output reinforces the logic level of 1 at Q. Consequently, as long as the two inverters remain powered, they maintain a stable state, continuously reinforcing each other's outputs. This cross-coupling of inverters enables the SRAM bitcell to reliably hold the stored bit without the need for refresh cycles, unlike DRAM. The robustness of this latch mechanism is a key feature that enables SRAM to retain data for as long as power is supplied.
Figure 0162b. Standard sRAM bitcell. |
[1] Ikeda, S., Yoshida, Y., Ishibashi, K., & Mitsui, Y., Failure Analysis of 6T SRAM on Low-Voltage and High-Frequency Operation. IEEE Transactions on Electron Devices, 50(5), 1270–1276, 2003.
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