Classification of Defects in ICs
- Integrated Circuits and Materials -
- An Online Book -

Integrated Circuits and Materials                                                                                   http://www.globalsino.com/ICsAndMaterials/     

Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix


=================================================================================

Table 4300a lists the classifications of defects in ICs. The classifications can be used in defect, fail, and PFA Pareto of yield detractors. An important objective of defect recognition, including defect detection and defect classification, is the early identification of process problems. [11] Removing systematic defects requires a series of processes:
         i) (Automatic or manual) detection. Defect detection includes removing the random defects from the measured data (denoising).
         ii) (Automatic or manual) classification. Defect classification includes sorting systematic defects into a set of predefined and meaningful categories. The defect patterns on a wafer provide useful information which can be used to highlight potential manufacturing problems as listed in Table 4300a.

Traditionally, the problem of defect recognition has been addressed through visual inspection by quality engineers using SEM. This manual approach leads to numerous misidentifications and is expensive in terms of personnel costs. A statistical procedure can routinely examine the patterns of failed chips wafer-by-wafer to identify the size, shape and location of clustered defects, and flags wafers or lots that exhibit significant spatial clustering.

Table 4300a. Classifications of defects in ICs.

Classification Defect Characteristics Sub-set of defect Characteristics of sub-set of defect Classification technique  
Random or systematic [8-9] Random point defects Are often regarded as being due to problems in the clean room and tend to rise and fall with the overall cleanliness of the environment. Reducing random point defects needs a long-term gradual improvement in clean room operation protocols or an expensive equipment overhaul. [9]        
Systematic point defects Systematic defects caused by assignable cause are usually attributed to process equipment
faults and/or human mistakes. Removing systematic defects requires a series of automatic detection and classification processes [9]		        
Global or local Global defects Random causes such as particles in the cleanroom generate global defects, which are scattered all over the wafer and are very expensive to correct [3]        
Local defects (clusters) Local defects are generated by assignable causes, e.g., human mistakes, particles from equipment, and chemical stains. These assignable causes are local destructive mechanisms that generate sets of aggregated defects or local defect clusters. [2, 4, 5] The specific patterns of local defect clusters reflect defect generation mechanisms. The spatial patterns of locally clustered defects therefore contain valuable information about defect generation mechanisms; therefore, methods for detecting local defect clusters and identifying their spatial patterns are highly desirable. [3]

Amorphous

Particles from equipment and chemical stains may generate amorphous defect clusters [6]

 MVN (Multivariate Normal Distributions) [3, ICspage2415]  
Center (bulls eye) If the pattern is located around the wafer center (bulls eye), it may be a result of nonuniformities created in the thin film deposition process or an uneven temperature distribution during the rapid thermal annealing process. [14]  

 
Circular ring A circular ring is due to problems in the etching step [10] SS (Spherical Shells) [3, ICspage2415]  
Clustered point defects

Clustered point defects on a wafer are usually due to process problems or human mistakes, information about cluster size, geometric shape, and spatial location is extremely valuable to process engineers seeking to recognize potential production problems

    
Curvilinear Clusters with curvilinear patterns may be caused by scratches [3] PC (Principal Curves) [3, ICspage2415]  

Edge (circular ring)

 If the pattern is located along the wafer’s edge (circular ring), it may be a result of nonuniformities created in the thin film deposition process or an uneven temperature distribution during the rapid thermal annealing process. [14] SS (Spherical Shells) [3, ICspage2415]

 
Elliptical zone

An elliptical zone often arises due to problems in thin film deposition process [10]

   
Linear scratch A linear scratch is a result of machine handling problems [12-13] MVN (Multivariate Normal Distributions) [3, ICspage2415]  
Ring-shaped
patterns		   SS (Spherical Shells) [3, ICspage2415]  

 

The defects in IC devices and the related failure can be very complicated and be categorized as listed in Table 4300b.

Table 4300b. Categories of defects in IC devices and the related failure.

Failure factor
Failure mechanism
Short
Open
Leakage
Decreased breakdown voltage
Vt or hFE shift
Unstable
operation
Resistance
fluctuation
Voltage plane shorts
                
Blislers
                
Edge chipping
                
Substrate distortion
                
Missing patterns
 Missing layers × ×          
          ×    
  × × ×     × ×
Incomplete etching
   × × ×        
Buried defects
External materials × × × × × × ×
Substrate, diffusion, P-N junction, Isolation
 Crystal defect ×   × ×   × ×
Crack   × × × × × ×
Surface contamination     × × × × ×
Junction deterioration ×   × ×      
Impurity precipitation ×   × × ×    
Photoresist mask misalignment × × × ×   ×  
Oxide film, gate oxide film, field oxide film
 Mobile ion     × × × ×  
Pinhole     × × ×    
Interface level     × × × ×  
Time dependent dielectric breakdown (TDDB) ×   ×        
Hot carrier     × × ×    
Metallization, on-chip wiring, via, contact, interconnection, contact hole, via hole
 Scratch × ×         ×
Void damage × ×         ×
Mechanical damage × ×         ×
Step coverage × ×         ×
Corrosion   × × ×   × ×
Insufficient adhesion strength   ×       × ×
Electromigration × ×         ×
Stress migration   ×         ×
Alloy pitting ×         ×  
Non-Ohmic contact   ×       × ×
Non-uniform or improper
thickness		             ×
Scar × ×          
Al projection due to Al-Si alloy formation ×         ×  
Al shift caused by resin stress   ×         ×
Bridging of W-plugs through W-extrusion [1] ×            
Via × ×          
Passivation, surface protective film, inter-layer dielectric film
 Pinhole ×   × × × ×  
Non-uniform thickness (step coverage block) × ×          
Unstable physical film-characteristics       × × × ×
Crack ×   × × × ×  
Contamination     × × × × ×
Reversed surface     × × × × ×
In most cases, the feature sizes of failure locations are on the order of a tenth of a micron or larger. However, the scaling of devices can increase their sensitivity of electrical performances to process variation, and thus root causes of failures can be localized to an extremely small size-scale, where only TEM has such spatial resolution.

 

==============================================================================================================================================

         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         
         

 

 

 

 

 

 













































































 

 

Table 4811a. Fab flow and properties of DRAM capacitors.

                                                     
                                                    Reference
                                                     
                                                     
                                                     
                                                     
                                                     
                                                     
       



                                           
                                                     
                                                     
                                                     
                                                     
a.




























 

Table 4834b. xx.

     
     
     
     
     

 

For

 

 

 

 


[1] Z.G. Song, G. Qian, J.Y. Dai, Z.R. Guo, S.K. Loh, C.S. Teh, S. Redkar, Application of contact-level ion-beam induced passive voltage contrast in failure analysis of static random access memory, in: Proceedings of the Eighth International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, Singapore, 2001, p. 103.
[2] J. Y. Hwang and W. Kuo, “Model-based clustering for integrated circuits yield enhancement,” Eur. J. Oper. Res., vol. 178, no. 1, pp. 143–153, 2007.
[3] Tao Yuan, Way Kuo, and Suk Joo Bae, Detection of Spatial Defect Patterns Generated in Semiconductor Fabrication Processes, IEEE Transactions on Semiconductor Manufacturing, 24(3), (2011), 392.
[4] F. L. Chen and S. F. Liu, “A neural-network approach to recognize defect spatial pattern in semiconductor fabrication,” IEEE Trans. Semiconduct. Manuf., vol. 13, no. 3, pp. 366–373, Aug. 2000.
[5] C. H. Wang, W. Kuo, and H. Bensmial, “Detection and classification of defects patterns on semiconductor wafers,” IIE Trans., vol. 39, no. 12, pp. 1059–1069, 2006.
[6] S. S. Gleason, K. W. Tobin, T. P. Karnowski, and F. Lakhani, “Rapid yield learning through optical defect and electrical test analysis,” Proc. SPIE-Int. Soc. Opt. Eng., vol. 3332, pp. 232–242, 1998.
[7] Friedman, D.J., Hansen, V.N. and David, A.J. (1997) Model-free estimation of defect clustering in integrated circuit fabrication. IEEE Transactions on Semiconductor Manufacturing, 10, 344–359.
[8] D.J. Friedman; M.H. Hansen; V.N. Nair; D.A. James, Model-Free Estimation of Defect Clustering in Integrated Circuit Fabrication, IEEE Transactions on Semiconductor Manufacturing, 10(3), (1997), DOI: 10.1109/66.618208.
[9] Hansen, M.H., Friedman, D.J. and Nair, V.J. (1997) Monitoring wafer map data from integrated circuit fabrication process for spatially clustered defects. Technometrics, 39(3), 241–253.
[10] Chih-Hsuan Wang , Way Kuo & Halima Bensmail (2006) Detection and classification of defect patterns on semiconductor wafers, IIE Transactions, 38:12, 1059-1068, DOI: 10.1080/07408170600733236.
[11] Chou, P.B., Rao, A.R., Sturenbecker, M.C., Wu, F.Y. and Brecher, V.H. (1997) Automatic defect classification for semiconductor manufacturing. Machine Vision and Applications, 9, 201–214.
[12] Chen, F.L. and Liu, S.F. (2000) A neural-network approach to recognize defect spatial pattern in semiconductor fabrication. IEEE Transactions on Semiconductor Manufacturing, 13, 366–372.
[13] Liu, S.F., Chen, F.L. and Lu, W.B. (2002) Wafer bin map recognition using a neural network approach.International Journal of Production Research, 40, 2207–2223.
[14] Hansen, M.H., Friedman, D.J. and Nair, V.J. (1997) Monitoring wafer map data from integrated circuit fabrication process for spatially clustered defects. Technometrics, 39(3), 241–253.

 

 

=================================================================================