Electron microscopy
 
Failure due to Cobalt Silicide Stringers and Spikes
- Practical Electron Microscopy and Database -
- An Online Book -
Microanalysis | EM Book                                                                                   http://www.globalsino.com/EM/        


=================================================================================

 

Cobalt silicide stringer, causing gate to drain leakage, had been observed in MOS structures as shown in Figure 1292a.

Cobalt silicide stringer causing gate to drain leakage

Figure 1292a. Cobalt silicide stringer causing gate to drain leakage [1].

Abnormal CoSix spikes under cobalt silicide film were also found in IC devices (e.g. Figure 1292b). Such spikes and Si/silicide interface roughness and thus various defects can cause unacceptable high junction leakage (junction shorting) because the spikes encroach on the junction edge when the silicide thickness becomes larger [3, 4]. In this case, the consumed silicon depth gets too large so that the silicide-silicon interface gets too close to the p-n junction. Goto et al. proposed that the leakage was driven by an area effect as opposed to perimeter effects [5, 6]. They stated that the leakage occurred at the phase transition temperature from Co2Si to CoSi as a results of CoSi spikes through the metallurgical junction. The stress-induced Co2Si/CoSi/Si triple points, leading to area spiking, result in significant junction leakage in ultra-shallow junctions. In fact, this leakage is caused by junction depletion region encroachment upon the silicide-silicon interface. On such failing samples, it was observed by AFM measurements that the surfaces of p+ diffusion areas were smoother than the n+ diffusion areas after the cobalt silicides had been removed with dilute HF [3].

Abnormal cobalt silicide spike

Figure 1292b. Abnormal cobalt silicide spike [2].

Note that, for ultra-shallow contact areas, it is critical to form smooth, conformal cobalt disilicide (CoSi2) without facets or voids for microelectronic device reliability. [8] On the other hand, to maintain the junction leakage within the tolerable range, the silicon consumption depth is limited to half of the source/drain contact junction depth. [7]

 

 

 

 

 

 

 

[1] ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis.
[2] ISTFA 2006: Proceedings of the 32nd International Symposium for Testing and Failure Analysis, November 12-16, 2006, Renaissance Austin Hotel, Austin, Texas, USA.
[3] Cor L. Claeys, ULSI Process Integration: Proceedings of the First International Symposium.
[4]Yoshio Nishi, Robert Doering, Handbook of Semiconductor Manufacturing Technology, 2000.
[5] K. Goto et al. A comparative study of leakage mechanism of Co and Ni salicide processes. Proceedings of the International Reliability Physics Symposium (IRPS), 1998; 363-369.
[6] K. Goto et al. Leakage mechanisms and optimized conditions of Co salicide process for deep sub-micron CMOS devices. Proceedings of the International Electron Device Meetings (IEDM) Technical Digest, 1999; 779-452.
[7] Park Yoon Soo, Shur Michael S, Tang William, Frontiers in Electronics: Future Chips, Proceedings of the 2002 Workshop on Frontiers in Electronics (Wofe-02) (Selected Topics in Electronics and Systems).
[8] Jing Yang, Jun Feng, Kecheng Li, Harish B. Bhandari, Zhefeng Li, and Roy G. Gordona, Quantitative Evaluation of Cobalt Disilicide/Si Interfacial Roughness, ECS Journal of Solid State Science and Technology, 6 (5) P345-P349 (2017).

 

 

 

 

=================================================================================