Comparison between Different Memories

Comparison between Different Memories
- Practical Electron Microscopy and Database -
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Table 3341 presents the comparison between different baseline and prototypic memories.

Table 3341. Comparison between different memories. The best performances in different ages are labeled in green.

		Baseline technologies						Prototypical technologies					Emerging
		DRAM		SRAM	Floating gate		HDD	Trapping charge	FeRAM	MRAM	RRAM	PCM /PRAM /PCRAM	STT-MRAM	Emerging ferroelectric	Redox memory	Mott memory	Macro-molecular memory	Molecular memory	Nano-mechanical memory	Graphene NVM	Graphene switch device
		Stand-alone	Embedded	SRAM	NOR	NAND	HDD	Trapping charge	FeRAM	MRAM	RRAM	PCM /PRAM /PCRAM	STT-MRAM	Emerging ferroelectric	Redox memory	Mott memory	Macro-molecular memory	Molecular memory	Nano-mechanical memory	Graphene NVM	Graphene switch device
Storage mechanism		Charge on a capacitor		Inter-locked state of logic gates	Charge trapping induced floating gate potential increase			Charge trapped in gate insulator	Remnant polarization on a ferroelectric capacitor	Magnetization of ferromagnetic layer: Vary the electric resistance of the resistor by manipulating the electron spin	Under debate	Reversibly changing amorphous and crystalline phases								Charge trapping induced gate potential increase	Vary the electric resistance of the graphene channel by oxidizing the channel graphene
Cell elements		1T1C		6T	MOSFET with a charge trapping stack (1T)			1T	1T1C	A switchable resistor and a (or two) transistor(s): 1(2)T1R	A Ti/TiO2 /Ti resistor and a selector (1D1R)	A chalcogenide resistor and a selector (1D1R) or 1T1R								Graphene FET with a charge trapping stack	Graphene FET
Feature size (F, nm)	2009	50	65	65	90	90	N/A	50	180	130	N/A	65
Feature size (F, nm)	2024	0	20	10	10	18		10	65	16	N/A	0
Cell area	2009	6F²	(12-30)F²	140F²	10F²	5F²	(2/3)F²	(6-7)F²	22F²	45F²	6F²	16F²
Cell area	2024	4F²	(12-30)F²	140F²	10F²	4F² - 5F²		(9-10)F²	12F²	8F² - 16F²	4F²	4F² - 6F²
Scalability									Bad			Best	Good	Good	Best	Unknown	Unknown	Best	Bad
Scalability limit		Capacitor		6T (4T possible)	Tunnel oxide/HV				Polarized capacitor	Current density		Litho-graphy limit							Litho-graphy limit
MLC		No		No	Best	Best		Best	Bad/no		Good	Best	Bad	Bad	Best	Unknown	Good	Bad	Bad
3D integration		No		No	Possible				Bad	N/A		Best	Good	Bad	Good	Unknown	Best	Bad	Bad
Density		~8 Gb/chip		N/A	N/A	64 Gb/chip	400 Gb/in²	N/A	128 Mb/chip	32 Mb/chip	64 Kb/chip	512 Mb/chip
Read time	2009	<10 nS	1 nS	0.3 nS	10 nS	50 nS	~8.5 ms	14 nS	45 nS	20 nS	~20 nS - µS	60 nS
Read time	2024	<10 nS	0.2 nS	70 nS	1.5 nS	8 - 60 nS	~8.5 ms	2.5 nS	<20 nS	<0.5 nS	~20 nS - µS	<60 nS
W/E time	2009	<10 nS	0.5 nS	0.3 nS	1 µS /10 mS	1/0.1 mS	~9.5 mS	20 µS/20 mS	10 nS	20 nS	~ 10 - 80 nS	50/120 nS
W/E time	2024	<10 nS	0.15 nS	70 pS	1 µS /10 mS	1 mS/ 0.1 mS	~9.5 mS	~10 µS/ 10 mS	1 nS	<0.5 nS	~ 10 - 80 nS	<50 nS								10ms/30ms	80μs/80μs
Retention time	2009	64 mS	64 mS	[A]	>10 y	>10 y	N/A	>10 y	>10 y	>10 y	>10 y (Good)	>10 y	Best	Best	Best	Good	Bad		Bad
Retention time	2024	64 mS	64 mS	[A]	>10 y	>10 y (Good)	N/A	>10 y	>10 y	>10 y (Very good)	>10 y	>10 y (Very good)								Good	~2 days
Write cycles (Endurance)	2009	>10¹⁶	>10¹⁶	>10¹⁶	>10⁵	10⁴ - 10⁵		10⁵	10¹⁴	>10¹⁶	~10⁶ - 10¹²	10⁹
Write cycles (Endurance)	2024	>10¹⁶	>10¹⁶	>10¹⁶	>10⁵	>10⁵		10⁶	>10¹⁶	>10¹⁶	~10⁶ - 10¹²	10¹² - 10¹⁵									≥ 8
Write operating voltage (V)	2009	2.5	2.5	1	12	15		7-9	0.9-3.3	1.5		3
Write operating voltage (V)	2009	1.5	1.5	0.7	12	15		4-6	0.7-1	<1.5		<3
Read operating voltage (V)	2009	1.8	1.8	1	2	2		1.6	0.9-3.3	1.5		3
Read operating voltage (V)	2024	1.5	1.5	0.7	1	1		1	0.7-1	<1.8		<3
Write energy (J/bit)	2009	5x10^-15	5x10^-15	7x10^-16	>10^-14	>10^-14		10^-13	3x10^-14	1.5x10^-10	~2 pJ	6x10^-12
Write energy (J/bit)	2024	2x10^-15	2x10^-15	2x10^-17	>10^-15	>10^-15		>10^-15	7x10^-15	1.5x10^-13	~2 pJ	<2x10^-13
Volatility		Yes	Yes	Yes		Not			Not	Not		Not
Program power						Low				Medium	Medium	Low								High	High
Fabrication cost									Good			Best	Good	Good	Good	Unknown	Best	Unknown	Bad
Comment									Destructive read-out	Spin-polarized write has a potential to lower write current density and energy
Reference		[1, 2]	[1, 2]	[1]	[1]	[1]		[1]	[1]		[1 - 3]	[1, 3]		[1]		[1]	[1]	[1]		[4]	[5]

* [A] SRAM memory state is preserved so long as the voltage is applied.

[1] The International Technology Roadmap for Semiconductors: Emerging research devices: (2009).
[2] Gang Zhang, Tian-Zi Shen, Hua-Min Li, Dae-Yeong Lee, Chang-Ho Ra, and Won Jong Yoo, Electrically Switchable Graphene Photo-Sensor using Phase-Change Gate Filter for Non-Volatile Data Storage Application with High-Speed Data Writing and Access, 2011 IEEE International Electron Devices Meeting (IEDM), DOI:10.1109/IEDM.2011.6131476, (2011).
[3] S. Lai et al., “OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications,” in IEDM Tech. Dig., 2001, s36p5, pp. 803-806.
[4] S. M. Kim et al., “Non-volatile graphene channel memory (NVGM) for flexible electronics and 3D multi-stack ultra-high -density data storages,” in Symp. VLSI Tech. Dig., 2011, t6b2, pp. 118-119.
[5] T. Echtermeyer et al., “Nonvolatile switching in graphene field-effect devices,” IEEE Electron Device Letts., vol. 29, no. 8, pp. 952-954, 2008.

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