This book (Practical Electron Microscopy and Database) is a reference for TEM and SEM students, operators, engineers, technicians, managers, and researchers.

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Passive voltage contrast (PVC) method for failure localization on semiconductor circuits  is based on contrast differences in FIB or SEM images of more or less electrically conducting structures in the circuits [1–7]. “Passive” is named because the IC die does connect to any power supply or signal sources. Therefore, failure localization with PVC is based on the fact that the floating conductive structure is charged up under the irradiation of the primary beam in FIB and SEM.

[1] J. Colvin, in Proceedings of the 16th International Symposium on Testing and Failure Analysis. A new technique to rapidly identify low level gate oxide leakage in field effect semiconductors using a scanning electron microscope, vol 331 (1990)
[2] N. Nishikawa, N. Kato, Y. Kohno, N. Miura, N. Shimizu, in ISTFA 1999 Proceedings. An application of passive voltage contrast (PVC) to failure analysis of CMOS LSI using secondary electron collection (1999), pp. 239–243
[3] C. Yuan, S. Li, A, ISTFA 2005 Proceedings. Gray method of failure site isolation for flash memory device using FIB passive voltage contrast techniques (2005), pp. 202–205
[4] C.M. Shen, S.C. Lin, C.M. Huang, H.X. Lin, C.H. Wang, ISTFA 2005 Proceedings. Couple passive voltage contrast with scanning probe microscope to identify invisible implant issue (2005), pp. 212–216
[5] T. Sakai, N. Oda, T. Yokoyama, in IEEE International Symposium 1999. Defect isolation and characterization in contact arraychain structures by using voltage contrast effect (1999)
[6] J. C. Lee, C. H. Chen, D. Su, J.H. Chuang, in ESREF 2002. Investigation of sensitivity improvement on passive voltage contrast for defect isolation (2002)
[7] R. Rosenkranz, in 8th European FIB User Group Meeting 2004. FIB voltage contrast for failure localization on CMOS circuits - an overview (2004)