Chapter/Index: Introduction | A |
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F |
G |
H |
I |
J |
K |
L |
M |
N |
O |
P |
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U |
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W |
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Appendix
Challenges in In-Line SEM Inspection on Wafers
| There are some challenges faced by chip designers as they push toward smaller and more complex structures in semiconductor manufacturing, specifically focusing on shrinking feature sizes and utilizing vertical stacking (as seen in 3D architectures). [1] These advances introduce new difficulties in defect inspection and metrology, with three critical challenges mentioned:
- Detecting defects at the bottom of deep holes and trenches: As devices go vertical (e.g., 3D NAND and FinFETs), structures like deep holes and trenches are harder to inspect because of their narrow and deep profiles. Tools need to be able to reach and detect defects at these hard-to-access locations.
- Finding sub-5 nm pattern defects: As feature sizes continue to shrink to the nanometer scale, it becomes increasingly challenging to identify defects that are smaller than 5 nm. Traditional inspection methods may lack the resolution needed to spot these defects, pushing the need for new or enhanced techniques.
- Maximizing defect sensitivity while maintaining throughput for wafer coverage: Increasing sensitivity to detect small defects often comes at the expense of inspection speed. The challenge is to strike a balance where inspection tools can detect even the smallest defects without sacrificing throughput, which is critical for maintaining production efficiency.
Figure 0009a. Detecting defects at the bottom of deep holes and trenches. [1] |
Figure 0009b. Finding sub-5 nm pattern defects. [1] |
| Figure 0009c. Maximizing defect sensitivity while maintaining throughput for wafer coverage. [1] |
The use of deep learning algorithms can enhance defect detection in semiconductor manufacturing. Deep learning has the potential to discover subtle defects that traditional inspection methods might miss.
[1] eSL10™ E-beam Wafer Defect Inspection System, KLA Corp.
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