Static random-access memory (SRAM or static RAM) is a type of semiconductor memory that uses bistable latching circuitry to store information. A typical DRAM bit cell contains of 4–8 transistors.

In SRAMs, a single word-line is divided into several ones by the sub-wordline drivers (SWL). Every SWL has to be selected by the main word-line (MWL) and the row select line signal (RX). Thus, only a partial word-line will be activated.

Figure 3295 shows a six-transistor CMOS SRAM bit cell. Each bit in an SRAM is stored on the four transistors (M₁, M₂, M₃, and M₄) that form two cross-coupled inverters. This storage cell has two stable states (0 and 1). Two additional access transistors (M₅ and M₆) control the access to the storage cell during read and write operations.

Figure 3295. A six-transistor CMOS SRAM bit cell: (a) Layout [1]; (b) Schematic illustration.

[1] Alex A. Volinsky, Larry Rice, Wentao Qin, and N. David Theodore, FIB failure analysis of memory arrays, Microelectronic Engineering 75 (2004) 3–11.