This book (Practical Electron Microscopy and Database) is a reference for TEM and SEM students, operators, engineers, technicians, managers, and researchers.
Cobalt silicidation can induce void formation at the edge of oxide pattern  and at the edge of the sidewall spacer of MOSFET devices . The void formation during post-annealing is favorable in reducing both the number of excess silicon vacancies and the tensile stress generated in the silicon substrate during silicidation. Cobalt silicidation generates Si vacancies in the adjacent Si region that is in contact with cobalt disilicide layer.  On the other hand, boundaries, e.g. free surfaces at STI (shallow trench isolation) and sidewall spacer edge, could lower the nucleation barrier for voiding. The void can cause serious junction leakage  or serve as a resistance in the current–voltage characteristics of devices .
Byun et al.  reported that the second RTA (rapid thermal annealing), which was used to convert cobalt monosilicide (CoSi) to cobalt disilicide (CoSi2), induced rapid silicon migration from silicon to cobalt monosilicide, resulting in a void. Figure 2796 presents a cross-sectional TEM image taken along  direction showing voids generated at the edge of the sidewall spacer of a MOSFET structure during post-annealing at 850 °C for 60 min.
Figure 2796. Cross-sectional TEM image taken along  direction showing voids generated during post-annealing at 850 °C for 60 min.
Pramanick et al.  observed that the voids existed at the Co/Si → CoSi2, CoSi2 → CoSi, and CoSi → CoSi2 phase boundaries.
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